FreeCores was started to provide a place for the sharing and development of free/libre open-source hardware designs, in the spirit of freedom.
FreeCores was formed in 2007 partially in response of the announcement that OpenCores could be going commercial; but having seen the good job done by the guys at ORSoC (who acquired the OpenCores website and community) now we think there's still no need for a fork at the moment.
There was a mailing list available on the freecores sourceforge site, but it has never worked properly...
Now this site acts only as a pointer to selected free/libre open-source cores.
Using one of the selected CPUs above and some of the other free cores available, it is possibile to design a complete microprocessor.
A summary of the specs of such a micro are detailed in the following table:
| Core | For FPGA processor | For ASIC processor |
|---|---|---|
| Target frequency | 100 MHz | 400 MHz |
| Selected CPU | 1 | 1 |
| Number of TLB entries for CPU above | 16 | 64 |
| Cache Controllers (L1-I$ + L1-D$ + L2-U$) | 1+1+1 | 1+1+1 |
| Size of L1 caches (I$+D$) | 4 KB + 2 KB | 16 KB + 8 KB |
| Size of L2 cache (unified) | 16 KB | 64 KB |
| SDRAM Memory Controller (mem_ctrl) | 2 | 2 |
| Programmable Interrupt Controller (simple_pic) | 1 | 1 |
| PWM/Timer/Counter (ptc) | 1 | 1 |
| General Purpose I/O (gpio) | 1 | 1 |
| DMA Controller (wb_dma) | 1 | 1 |
| UART 16550 (uart16550) | 2 | 4 |
| FastEthernet MAC (ethmac) | 1 | 1 |
| SD/MMC Controller (spimaster) | 1 | 1 |
| SD/MMC FPGA Config (fpgaconfig) | 1 | 0 |
| USB 1.1 Host and Function (usbhostslave) | 1+1 | 1+1 |
| AC'97 Audio Controller (ac97) | 1 | 1 |
| VGA/LCD Controller (vga_lcd) | 1 | 1 |
FreeCores has been sponsored by Simply RISC:
